A delay locked loop (DLL) corrects a duty cycle error of an input clock signal to generate an output clock signal that is synchronized with the input clock signal.
Generally, a semiconductor memory device includes a delay locked loop such that the semiconductor memory device outputs data in synchronization with an input clock signal. For example, the delay locked loop may generate an output clock signal, which is synchronized with the input clock signal, and the semiconductor memory device may output the data in synchronization with the output clock signal such that the data is provided in synchronization with the input clock signal. Therefore, as an operation speed of a semiconductor memory device increases, a delay locked loop operating in a high speed is often used.
If a delay locked loop corrects a duty cycle error of an input clock signal in a digital manner, an accuracy of the delay locked loop decreases. Alternately, if a delay locked loop corrects a duty cycle error of an input clock signal in an analog manner, an operation speed of the delay locked loop decreases.